SMART Photonics offers our customers access to our technology by our Multi-Project Wafer service (MPW). An important advantage of generic integration processes is that designs from different users can be combined on a single wafer, a so called Multi-Project Wafer (MPW).
Sharing mask and wafer resources reduces the costs of prototyping and the number of design cycles is smaller because the process is mature and designers can use a library of proven components. Further, scaling up to larger volumes is straightforward, because the prototype has been developed in a industrial process. This leads to a large reduction of the entry costs for new PIC users and brings Photonic Integration within reach.
Would you like to participate in one of SMART Photonics Multi-Project Wafer runs and do not know where to start?
Please follow the 4 steps defined below:
Your chip ready in 4 steps
- Get in touch
Contact SMART Photonics to express your interest. We are interested to learn about your wishes and requirements.
- Sign the Non Disclosure Agreement
The NDA is protecting your ideas when sharing and exchanging valuable design information with us and our brokering partner who is responsible for the secured server. When the NDA is signed we will allow your software partner to submit our PDK.
- Design manual
The design manual is included in the PDK. Upon request we share our latest design manual for review.
- PDK
Request the Process Design Kit (PDK) from the software supplier of your choice. Currently the SMART Photonics PDK is implemented in the following software packages:
Synopsys (Optsim circuit and Optodesigner layout tool)
VPIphotonics (VPIComponentMaker circuit and layout via OptoDesigner, IPKISS and Nazca)
Luceda (IPKISS layout and circuit)
Lumerical (Interconnect circuit) (contact us for implementing the CML from Lumerical )
Nazca Design (Nazca design)
PhotonDesign (PICWave circuit)
- Design your chip
Everything is now in place to design your own Photonic Integrated Chip. Feel free to contact our design support team for design related questions.
- Reserve your spot
After (almost) finalizing your design, check the Multi-Project Wafer schedule on our website and choose the run on which you want to participate.
Upon receipt of your order and based on availability we will reserve your spot. The cell will be assigned 1-2 weeks before the design submission deadline.
Request the pricelist or quotation at sales@smartphotonics.nl.
- Submit design to the secured server
After the cell is assigned you will receive instructions per E-mail to upload your design.
- Design Rule Checks
In the 2 week period between design submission deadline and mask tape out we perform Design Rule Checks.
We will verify in up to 3 iterations if your design complies with the design rules in our manual, and provide the required and adviced improvements in a report.
- Manufacturing of chips
After mask tape out, the actual processing of the MPW will start. The processing will take up to six months. During this time SMART Photonics will inform you on a monthly basis by E-mail where your chip is in the process.
- Chip delivery
When the chips are ready they will be shipped to your delivery address. The tracking information and wafer verification report will be forwarded by e-mail.
OUR PARTNERS AND LINKS
- Synopsys (Optsim circuit and Optodesigner layout tool)
- VPIphotonics (VPIComponentMaker circuit and layout via OptoDesigner, IPKISS and Nazca)
- Luceda (IPKISS layout and circuit)
- Lumerical (Interconnect circuit) (contact us for implementing the CML from Lumerical )
- Nazca Design (Nazca design)
- PhotonDesign (PICWave circuit)
