Multi-Project Wafer service

SMART Photonics offers our customers access to our technology by our Multi-Project Wafer service (MPW). An important advantage of generic integration processes is that designs from different users can be combined on a single wafer, a so called Multi-Project Wafer (MPW).

Sharing mask and wafer resources reduces the costs of prototyping and the number of design cycles is smaller because the process is mature and designers can use a library of proven components. Further, scaling up to larger volumes is straightforward, because the prototype has been developed in a industrial process. This leads to a large reduction of the entry costs for new PIC users and brings Photonic Integration within reach.

Would you like to participate in one of SMART Photonics Multi-Project Wafer runs and do not know where to start?
Please follow the steps defined below:

How to engage

to  one of our collaboration partners.

JePPIX as brokerer for our technology, they can help you with design capability, software and packaging solutions.

Alternatively you may want to engage with a design house. There are currently two design houses that are very familiar with our platform. Engage with one of them to convert your ideas into a product (Bright Photonics, VLC Photonics).

To be able to share the design manual and process design kit one first needs to sign up for a Non Disclosure Agreement (NDA). This is protecting us as foundry and the IP that we have build up and going to share with you. But also vice versa, this document is protecting you when sharing and exchanging valuable design information with us and with one of our brokering partners that are responsible for the secured server.

When the NDA is in place you can request the design manual. Please send us an e-mail or request your copy by filling in this form.

Request access to a Process Design Kit (PDK) of your choice for circuit simulation and mask design

Currently the SMART Photonics PDK is implemented in the following software packages:

  • Synopsys (Optsim circuit and Optodesigner layout tool)
  • VPIphotonics (VPIComponentMaker circuit and layout via OptoDesigner, IPKISS and Nazca)
  • Luceda (IPKISS layout and circuit)
  • Lumerical (Interconnect circuit)
  • Nazca Design (Nazca design)
  • PhotonDesign (PICWave circuit)
  • Mentor Graphics (Tanner L-Edit layout) (check webinar)

Once you are getting close to submitting a design, please check the Multi-Project Wafer schedule. This is providing information on the upcoming runs. During the time that the run in in the fab, you can find the latest updates on your batch.

When you know which run you would like to participate, then please request a quotation or launch an order. When space is still available on the run, we will provide you with an order confirmation and a cell number that you can use to upload your design.

If you want to have a dedicated run on the platform you are not limited to the timing and can request independently from the MPW scheduling.

For the design storage SMART Photonics uses the secured JePPIX file server. JePPIX is a broker of our service and SMART Photonics is using this infrastructure which guarantees the revision control and secure upload of your design. If you have an account already you will receive your cell ID when you launched an order. When you don’t have an account yet, please request one here. Please also inform the SMART Photonics sales team that you have requested the account. When accepted by JePPIX SMART Photonics can assign you a cell number.

Once you are in the JePPIX system, the uploading is self-explanatory. When help is required, please reach out to one of our team members for support.

When timely submitting a design, SMART Photonics provides you with up to three free Design Rule Checks that can be used to improve the design and reduce errors.

In order to be able to support this service you can use these three DRChecks starting three weeks before the closing date of the MPW run. After this every week, one can submit an improved design to the secured server which allows for three iterations before the design will be frozen and masks will be assembled and ordered.

When the closing date is passed, one cannot make any changes any more since the final mask will be assembled and ordered. This is the actual start of the MPW run.

After this SMART Photonics will start with epitaxial growth, etching, regrowth, overgrowth, processing, metalizing, thinning, metalizing, cleaving, coating, chipping and validating of test cells.

This process with more than 1000 wafer handling steps will take up to four months. During this time one can check the MPW scheduling page for the actual progress and changes in delivery date

When the chips are ready for shipment, these will be send to the requested delivery address. In order to provide you with the fastest delivery, SMART Photonics will dispatch the chips but continue in the meantime characterizing the test cells and its performance and finalize the wafer verification report. When this is done you will receive that in your e-mail.

SMART PHOTONICS PROCESS DESIGN KIT (PDK)

The SMART Photonics PDK comprises of a comprehensive building block library, build up out of active and passive devices for InP based photonic integration. The SMART Photonics PDK is available for various software partners each with their own expertise in designing and simulating photonic ICs. Each building block of the PDK is regularly tested and calibrated from measurements to ensure correct optical and electrical performance at a circuit simulation level. The PDK enforces users to obey certain predefined design rules set by the fab, thereby removing the necessity for the user to gain in-depth knowledge and expertise required to fabricate a functional device. Circuit designs can be exported to a layout tool. In our ongoing collaboration with our software partners we are working towards standardizing this interface. This opens up the possibility to exchange photonic circuit designs between different software packages. Check our handout about the Process Design Kit.

OUR PARTNERS AND LINKS

  • Synopsys (Optsim circuit and Optodesigner layout tool)
  • VPIphotonics (VPIComponentMaker circuit and layout via OptoDesigner, IPKISS and Nazca)
  • Luceda (IPKISS layout and circuit)
  • Lumerical (Interconnect circuit)
  • Nazca Design (Nazca design)
  • PhotonDesign (PICWave circuit)
  • Mentor Graphics (Tanner L-Edit layout) (check webinar)

Sales Support

Vincent Kroeze Sales Support Engineer

Do you have a question or would you like to make an appointment? Send me a message!