Generic Integration Process

genericSMART Photonics has developed a generic process for the production of photonics integrated circuits. This has been done together with COBRA, the research division of the Institute for Photonic Integration.  This generic integration technology has brought a paradigm shift in way photonic integrated chips are produced. Generic integration causes a dramatic reduction in the entry costs when applying Photonic ICs in novel or improved products. It has brought these photon-based technologies within reach for many SMEs, as well as established international high-tech enterprises.

Simplifying the Chip Making Process

In electronics, you've been able to design chips using a process design kit (PDK) for decades. You build your design virtually, test and optimize it, knowing that what you send to be fabricated will perform in the way you expect. But making a PDK delivers more than just a model. You’re also connecting design software with process control, which is a method to understand and improve yields. With photonics, it hasn't been as easy. Photonic devices can interact and behave in complex ways. There may be instabilities that occur that you didn't expect. Until recently, you needed several trial runs before the fab can get their tolerances in spec. All that has now changed.

Thanks to the recently concluded Paradigm research project, we've now reached a stage where the SMART Photonics Process Design Kit can be used by any InP photonics chip designer. You don’t need an in-depth knowledge of the underlying technology or the fabrication process. All you need is a clear understanding of the end goal. In the journey from a software design to functional InP chips, there are hundreds of process steps, each of which may have dozens of parameters associated with them. We've now reached a point where we're able to offer process InP design kits at the building block level. This means that the same stable process can be used for many different circuits.

How the InP Process Design Kit works in practice

You pick your laser and place where you want it on the chip. Under the hood, there are sophisticated simulation tools which predict what a circuit will do, and layout tools which enable our fab to make it as intended.  All this reduces the number of test fabrication runs that need to be made before a new chip design matches the original performance specifications. And this helps reduce the hardware development costs.

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The brokering role of JePPIX

JePPIX is an organisation with over 250 members spread all over the world. It is crucial for effective coordination of this emerging eco-system. JePPIX tasks include:

  • Brokering: combining designs from different users in Multi-Project Wafer (MPW) runs via the JePPIX platform. The costs of R&D runs are shared by several users.
  • Organising detailed manuals and training for the foundry processes.
  • Reaching out to potential users, mentoring through the decision process and design-fabtest flow and identifying opportunities that the novel technology brings for their product portfolio.
  • Bringing them into contact with designers with relevant expertise in their field.
  • Setting the strategic roadmap and providing leadership in this new technology sector.

 Check the SMART Photonics Multi-Project Wafer schedule below for the deadlines and planning for the next series of runs.

MPW Schedule

The MPW schedule and updates are on a separate page


This is a short summary of various relevant publications.

SMART Photonics Application notes

Generic Integration Roadmap

Journal and conference contributions